The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to techniques for protecting device components from chemical-mechanical polish (CMP) induced substrate damage.
In semiconductor IC fabrication, devices such as component transistors are formed on a substrate, which may typically be made of silicon. Uses for the substrate may include, for example, the fabrication of ICs or flat panel displays. Successive layers of various materials may be deposited onto a substrate and selectively removed to form layered mesa structures on a silicon wafer. In a previously-filed patent application entitled "Self-Aligned Polysilicon FET Devices Isolated with Maskless Shallow Trench Isolation and Gate Conductor Fill Technology and Method of Manufacture Thereof," (Attorney Docket No. HQ9-96-051), filed May 1, 1997 (Ser. No. 08/515,714) and incorporated herein by reference, a layered mesa structure is described for isolating devices in the formation of FET devices fabricated in accordance with very large scale integration (VLSI) techniques. In general, a layered mesa structure may include pad layers, e.g., pad nitride and pad oxide layers, deposited over a silicon mesa (which may be single crystal silicon in structure). To facilitate discussion, FIG. 1 illustrates a layer stack 110, which may be formed on a substrate 112. A pair of mesas 114 and 116 are formed on substrate 112 by masking and etching a shallow trench into the substrate to form the silicon mesas. The resulting mesas are then capped with one or more pad layers.
As shown in FIG. 1, mesa structure 114 includes pad layers, some of which are shown as a pad nitride layer 118 overlying a pad oxide layer 120. Pad oxide layer 120 may be, for example, about 25-300 angstroms thick. Pad nitride layer 118 may be, for example, about 500 to about 2,500 angstroms thick. Likewise, mesa structure 116 includes pad layers, some of which are shown as a pad nitride layer 122 overlying a pad oxide layer 124. A dielectric layer 126, which may be TEOS or silicon dioxide, is shown conformally deposited over substrate 112 and the pad layers of mesa structures 114 and 116. This dielectric layer 126 may be, for example, about 3,000 to about 9,000 angstroms thick. The dielectric material disposed between the mesa structures provides the shallow trench isolation (STI) region to isolate devices of the mesa structures.
Above dielectric layer 126, there is disposed a polysilicon layer 130, representing the layer from which a mask may be formed to facilitate the subsequent etching of dielectric layer 126. The polysilicon may be, for example, about 2,000 to about 8,000 angstroms thick. FIG. 2 shows the substrate of FIG. 1 after a chemical-mechanical polish (CMP) step has been employed to planarize polysilicon layer 130 and silicon dioxide layer 126. The CMP process typically terminates when the high areas of silicon dioxide layer 126 break through polysilicon layer 130, and/or the exposed silicon dioxide layer is planarized to a specific design thickness (i.e., it is not always required that the CMP step terminates exactly when high areas of silicon dioxide layer 126 break through polysilicon layer 130). After CMP, the high areas of the dielectric layer are exposed through the polysilicon layer to facilitate dielectric etching while other areas of the substrate are masked off by the remaining polysilicon.
During CMP, however, the exposed surface of silicon dioxide layer 126 may be damaged by various CMP process defects. These CMP process defects include, for example, scratching and over-polishing. Scratching may occur when an abrasive particle comes between a CMP rotating pad and the exposed oxide surface. The rotational force and pressure of the pad against the abrasive particle may gouge the exposed oxide surface. This scratch is illustrated as scratch 200 over mesa structure 116. As can be seen in FIG. 2, the presence of scratch 200 decreases the thickness of the dielectric material above pad nitride layer 122.
Over-polishing may also produce thin areas of the dielectric layer and may result from improper CMP process parameters, which may include improper process duration, pad pressure, pad abrasiveness, brushing speed, slurry chemistry and other factors. When one or more CMP process parameters are incorrect it may not be possible to precisely control the material removal and a thinner than desired dielectric layer may be present over the mesa structure. dielectric etch has removed portions of the unprotected areas of silicon dioxide layer 126 to form hollows. During the dielectric etch, the regions of polysilicon layer 130 that were not removed by CMP act as a hard mask which protects the underlying dielectric material. Typically, the dielectric etch is designed (e.g., timed) to leave a controlled amount of dielectric material above the pad layer, e.g., above the pad nitride layer. By way of example, the dielectric etch may represent a partial reactive ion etching (RIE) or wet etch of the exposed surface of the dielectric material and remove about 2,000 to about 9,800 angstroms of silicon dioxide. With reference to FIG. 3, the dielectric etch is designed to form a hollow 302 in dielectric layer 126 and to leave a thin (e.g., about 800 to 900 angstroms thick) dielectric layer 320 above pad nitride layer 118 of mesa structure 114. However, where silicon dioxide layer 126 is thinner than intended due to CMP process defects (e.g., due to scratch 200 as shown in FIG. 2), the thinner silicon dioxide layer above the mesa may be completely etched through instead of only partially etched. Further, the previously disclosed dielectric etch chemistry, which typically includes a mixture of CHF.sub.3, CF.sub.4, and/or argon, permits the pad layer(s) (e.g., pad nitride 122 and pad oxide 124) to be etched through during this dielectric etch step, thereby exposing some of the underlying substrate 112 material (typically single crystal silicon in structure). The inadvertent etching of the pad nitride layer and the pad oxide layer is depicted above mesa structure 116 of FIG. 3. Due to the fact that the dielectric etch chemistry is typically selective to silicon (so as to avoid attacking the polysilicon hard mask), the underlying silicon substrate 112 is typically not attacked during this dielectric etch step even if the pad layers are inadvertently etched through.
To facilitate further processing, the polysilicon hard mask may then be removed. Because the polysilicon etchant (typically comprising SF.sub.6 and NF.sub.3) or wet etch employed to remove the polysilicon hard mask typically does not readily attack the dielectric material, layers underlying thin dielectric layer 320 (e.g., pad nitride layer 118, pad oxide layer 120, and the substrate materials underlying these layers) are protected during this polysilicon removal step. However, the polysilicon etchant readily attacks any silicon substrate material (e.g., single crystal silicon) exposed by a combination of CMP process defects and the CHF.sub.3 /CF.sub.4 /Ar dielectric etch or wet etch. With reference to FIG. 3, the substrate material at the region of mesa structure 116 would then be inadvertently etched away during the polysilicon removal step. The result is a CMP-induced substrate defect (which is shown as a void 402 in FIG. 4) in substrate 112 in the region of mesa structure 116.
This void may also be formed if the layer stack is over-polished during the CMP step such that a thinner-than intended dielectric layer is present above mesa structure 116 prior to the subsequent dielectric etch step. The result of over-polishing is depicted in FIG. 5, which shows a thinner layer of dielectric material overlying mesa structure 116 as compared to the layer of dielectric material overlying mesa structure 114. The presence of void 402 in the substrate may cause problems to devices subsequently formed. By way of example, void 402 may result shorting of the subsequently deposited gate conductors and/or gate oxide breakdown, which leads to gate-to-substrate, gate-to-ground shorts, etc.
In view of the foregoing, there are desired improved methods for protecting device components from CMP defect-induced etching damage during dielectric etching.